DDR3 2G 1066 /1333MHZ

Desktop memory:DDR3 2GB 1333Mhz PC3-10700 Specification: 1. Capacity: 2GB 2. Buss speed: 1333Mhz 3. Bandwidth:10700 4. Pins: 240 5. Interface:LONG DIMM 6. VDD: 1.8V(+/-0.1v) 7. Latency: 5 8. IC chips brands: OEM 9. Configuration: 128*8 or 256*8 Packing details and warranty: 1. bulk packing:25 pcs/box=0.5kgs 50pcs/box=1kgs 2. retail packing: 50pcs/big box=1.3kgs1000pcs/carton=26kgs 3. warranty:5years Delivery time and methods: 1. general speaking:1 5days 2. sample order delivery after the payment at the same day. 3. big order needs 3 5 days to prepare. 4. DHL , UPS or EMS. Payment terms: 1. 100% payment before delivery 2. more than usd2000: T/T 3. Less than usd2000: western union (for more details, pls contact me) Test report: Factory and company details: Certification: Computer RAMS: 1) Computer Ram DDR DDR2 DDR3 2) 168/184/240-pin socket type dual in line memory module (DIMM) 3) 2.6V power supply 4) Data rate: 400/333/533/667/800Mbps (max.) 5) 2.5 V (SSTL-2 compatible) I/O for DDR I products,1.8Vpower supply for DDR II products 6) Double-data-rate architecture, two data transfers per clock cycle 7) Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver 8) Data inputs and outputs are synchronized with DQS 9) DQS is edge aligned with data for read, center aligned with data for write 10) Differential clock inputs (CK and CK) 11) DLL aligns DQ and DQS transitions with CK transitions 12) Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 13) Four internal banks for concurrent operation (component) 14) Data mask(DM) for write data 15) Auto precharge option for each burst access 16) Programmable burst length: 2, 4, 8 17) Programmable/CAS latency (CL): 3 18) Programmable output driver strength: normal/weak 19) Refresh cycles: (8192 refresh cycles/64ms) 20) 7.8US maximum average periodic refresh interval 21) Posted CAS by programmable additive latency for better command and data bus efficiency 22) Off-chip-driver impedance adjustment and on-die-termination for better signal quality 23) DQS can be disabled for single-ended data strobe operation 24) 2 variations of refresh 25) Auto refresh 26) Self refresh