74LVC1G04GW - Single inverter - NXP Semiconductors

Philips Semiconductors Product specification Single inverter 74LVC1G04 FEATURES · Wide supply voltage range from 1.65 to 5.5 V · High noise immunity · Complies with JEDEC standard: – JESD8-7 (1.65 to 1.95 V) – JESD8-5 (2.3 to 2.7 V) – JESD8B/JESD36 (2.7 to 3.6 V). · ±24 mA output drive (VCC = 3.0 V) · CMOS low power consumption · Latch-up performance £250 mA · Direct interface with TTL levels · Inputs accept voltages up to 5 V · Multiple package options · Specified from -40 to +125 °C. DESCRIPTION The 74LVC1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 or 5 V devices. These features allow the use of these devices in a mixed 3.3 and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G04 provides the inverting buffer. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf £ 2.5 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in mW). PD = CPD ´ VCC 2 ´ fi + (CL ´ VCC 2 ´ fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay input A to output Y VCC = 1.8 V; CL = 30 pF; RL = 1 kW 3 ns VCC = 2.5 V; CL = 30 pF; RL = 500 W 2 ns VCC = 2.7 V; CL = 50 pF;