Smartcard-Chip: TP40 (Theseus Platinum 40)

Smart card chip: TP40 (Theseus® Platinum 40) is good chip as Pay TV card and SIM card. Features - Enhanced 8051- compatible core that operates on 4-clock cycles - ISO 7816-3 Serial interface compliant - 640 bytes of RAM (256 standard, 384 external RAM) - Software controlled Flash NVM - Extended memory addressing through banking - Interrupts to trap security violations - Software controlled power-saving options - User-friendly code loading process - Physical Memory Security Attributes - Customer3 or transport code software loading options Environment - Single 3 V or 5 V supply ± 10% - Operating temperature -25 0C to +85 0C - Maximum Supply current: - <6 mA@30 MHz - <10 mA@60 MHz - Low current Idle Mode - External clock frequency 1-10 MHz - Multiple clock sources that are user selectable: - Software controlled PLL with multiply by 1 to 16 - 60 MHz Internal Oscillator with divide by 1 to 16 - 4kV ESD Protection - ISO7816-2 compliant contacts Flash Non-Volatile Memories - All Flash NVM locations are Electrically Erasable Programmable Read Only Memory (EEPROM) - 40 Kbytes of Flash NVM (including 1K Locked System Memory) - 8 Kbytes of small page EEPROM - 32 Kbytes of large page UCM - UCM can operate as One-Time Programmable Read Only Memory (OTPROM) - Small page EEPROM available with 8 byte or 64 byte page erase - Large page UCM available with 512 byte page erase - UCM can be configured by user software to operate as: - EEPROM (Default) - OTPROM - Execute Only - Access to UCM controlled by physical memory security attributes - 10 year Data retention on all Flash NVM bytes - EE Memory guaranteed >100K Program/Erase cycles - 2 ms page erase time (typical) - 75 μs byte write time (typical) Security - Unique chip identification number - Out of Frequency detection - Out of Voltage detection - Out of Temperature sensors - Persistent NVM tampering flags accessible Performance - Enhanced 8051 offers 2.5x performance improvement over the standard 8051 - Ability to run core at 60 MHz - Dual data pointers to erase and speed up table handling - Increased execution and performance rates in bus cycling - Speed increase in instruction cycles - Dynamic switching between clock sources - Fast UCM code loading - Memory can be written byte-by-byte at very high speeds Development Environment - Supported by Rania®4 Simulator Rapid Development Environment - Programmable through Rania SwiftSIM®5 Programmer - Code compatible with Keil® compilers - Compatibility of development and implementation software tools Supported Standards - ETSI GSM 11.11 - ETSI GSM 11.12 - ISO 7816-3 compliant electrical interface Support - Application Notes and API Code Document References - Chip Qualification report - Chip delivery specifications (including packaging description) - Module Qualification report - Module delivery specifications (including packaging description)