Fieldbus Communication Controller

1.Brief Introduction Designed to comply with IEC 61158-2 Has physical layer and some function of link layer Good at integration, simple external circuit, small size Available in 44-pins TQFP package Internal 4k bytes asynchronous SRAM storage data for transmitting, receiving and address lookup table Low power consumption design<600UA Available for developing the products with FF H1,PROFIBUS PA 2.Performance Characteristic Supports line data rate 31.25K BIT/S Build-in Manchester Encoder/Decoder Transmitter Jibber inhibit, receiver super long frame inhibit Automatic parity recognition and correction Build-in two channels DMA controller,used to control data transmitting, receiving and address recognition Build-in bus arbiter, CPU accessing internal SRAM correctly Internal loop back for t: -40 85